The present invention relates, in general, to a system and method for write-protecting predetermined portions of a memory array. More particularly, the present invention relates to a system and method wherein a predetermined soft fuse value may be written to a corresponding soft fuse register to control subsequent access to a number of lock bits in a non-volatile semiconductor memory array which are provided for selectively precluding writes to predetermined portions of the memory array. In a specific embodiment, the system and method may be utilized in conjunction with radio frequency ("RF") identification ("ID") transponders incorporating a non-volatile ferroelectric random access memory ("FRAM.RTM.") array integrated circuit available from Ramtron International Corporation at Colorado Springs, Colo. assignee of the present invention.
A possible implementation of a passive RF transponder is described in U.S. patent application Ser. No. 08/194,616 entitled "PASSIVE RF TRANSPONDER AND METHOD" and a communication system utilizing frequency shift keying ("FSK") and pulse shift keying ("PSK") modulation techniques in conjunction with a passive RF transponder is described in U.S. patent application Ser. No. 08/194,723 entitled "COMMUNICATIONS SYSTEM UTILIZING FSK/PSK MODULATION TECHNIQUES" both filed on Feb. 10, 1994 and assigned to RACOM Systems, Inc. of Englewood, Colo. RACOM Systems, Inc. manufactures and sells the RFC100 CORE reader/writer electronics module controller and the RFM256 transponder, the latter of which comprises an integrated circuit device including a 16 word (32.times.8 bit) FRAM memory array manufactured by Ramtron International Corporation using a proprietary lead-zirconate-titanate ("PZT") ceramic thin film process.
The non-volatile FRAM memory array of the transponder utilizes a number of lock bits to write-protect certain areas of the memory array. In this particular implementation, the lock bits are located in the first four bit positions of word 0. In operation, if specific lock bits are set, "writes" are precluded to predetermined corresponding portions of the FRAM memory array making the information contained therein essentially unchangeable. On the other hand, if specific lock bits are not set, data can be written to the same memory word bit locations repeatedly, thereby "overwriting" or changing the data. Once the lock bits have been set, they may not be "unset" thereafter to ensure the integrity of the information at the corresponding memory array bit locations.
Upon fabrication of the integrated circuit for the RFM256, the individual lock bits of the memory array (as with all other bit locations in the memory array) may randomly assume one of two different states in accordance with the known operating characteristics of FRAM memory devices. That is, they may individually assume either a logic level "one"(or "set" condition) or logic level "zero"(or "unset" condition). Prior to shipment to the end user for encapsulation or integration with other circuitry or devices, the lock bits must be cleared to a consistently "unset" state such that they may later be set as appropriate once data is written to the memory array. Currently, the integrated circuit includes a test pad which is probed during wafer test to set and unset (or "toggle") the lock bits to test their functionality and to ensure that they actually lock as well as to effectively "clear" (or unset) them prior to shipment.
However, in addition to the on chip "real estate" consumed by the test pad, the time necessary to probe the wafer adds significantly to the processing and handling time of the integrated circuit die, and hence, increases its cost. Moreover, once the die has been encapsulated, for example in an RF transponder package, the test pad is no longer accessible to allow toggling of the lock bits to alter their state or determine whether encapsulation has rendered the die inoperative.